Job Description
-Participate in high speed SERDES PHY design, such as PCIE, USB and SATA.
-Will be involved in the whole ASIC design flow from RTL coding through P&R support, which includes logic design, DFT planning and implementation, logic synthesis, power optimization, static timing analysis and sign-off.
-Will also work closely with analog design teams on IP integration, with P&R engineers on chip floor planning and timing optimization, and with product/test engineers on ATE tests. Work closely with frontend and backend design teams, as well as test engineers.
Job Requirement
-BS or MS in EE/CS
-Excellent knowledge of RTL design and verification.
-Hands-on experience with Verilog, C/C++, Perl, Tcl.
-Experience in PCIE,USB and SATA is a plus.
【关于Marvell】
Marvell(纳斯达克代码：MRVL)是全球领先的完整芯片解决方案，旨在实现 “Smart Life and Smart Lifestyle”。Marvell公司拥有从存储、云基础设施、数字娱乐到家庭内容交付的多元化产品组合，将完整的平台设计与业界领先的性能、安全性、可靠性和效率相结合。作为消费电子、网络和企业系统的强大核心，Marvell公司令合作伙伴及其客户始终站在创新、性能和大众诉求的最前沿。Marvell公司致力于提高大众的生活体验，通过为世界各地的用户提供移动性和易于访问的服务，为社交网络、生活和工作增添价值。更多公司信息，请浏览公司网页 www.marvell.com.cn