RESPONSIBILITIES: - Implement SOC DFT function including SCAN,Boundary SCAN, MBIST, Analog Macro test logic. - Perform verification on all DFT structures - Generate DFT related timing constraints and workwith PD team for timing closure - Generate and verify DFT structural patterns andfunctional patterns - Participate in ATE bring-up and debug the DFTpatterns on ATE - Design and implement other DFX (debug,characterization, yield etc) logics REQUIREMENTS: - Master degree in EE/CS with at least 12 years’experience, or Bachelor degree with at least 15 years’ experience in IC orsemiconductor industry - Minimum 7 years of experience in DFx-relatedareas - Hands on working experience on ASIC DFT designand verification, familiar with entire ASIC design flow - Strong analytical/problem solving skills andpronounced attention to details. - Must be a self-starter and able to independentlydrive tasks to completion. - Strong interpersonal and communication skills
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