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军衔等级:

  上等兵

注册:2009-4-27
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发表于 2009-4-27 22:18:57 |只看该作者 |倒序浏览
SoC Verification Engineer
Location :shanghai/hangzhou

Job Description

        Understandes functional and design specification for SoC (ASIC/FPGA)
        Generates the test bench modules and scripts for verification
        Develops test cases according to test case definition.
        Is responsible for test script development and maintenance
        Simulates the needed functionality on Top-Level
        Ensures effective testing and high quality product delivery.
        Report and analyze product's defects
        Prepares and reviews System-on-Chip test documentation

Job Requirements:

SoC development & Methodology

        2+ years of SoC (ASIC/FPGA) verification experience
        Very good HDL"  class="t_tag">VHDL/Verilog knowhow and coding and modeling experience
        Excellent knowledge of SoC (ASIC/FPGA) verification tools.
        Understanding of the SoC (ASIC/FPGA) design flow and process.
        Knowledge of SoC (ASIC/FPGA) design tools

System
One to Two skills as mentioned below is required:

Solid background in Protocol testing (SW featurelevelverification),functional testing (overall feature in differentsystemconfigurations)and performance testing (environmental, EMC,safety)related personsneeded.
        Background in Cellular networks and 2G and 3G technology
        Knowledge on TDM and Packet (IP/Ethernet) based telecommunication network solution
        Knowhow in Microwave radio transport.
        Understanding of SDH and PDH technology and interfaces.

Experience
        2+ years experience in the R&D of Telecommunication Networks or Communication industry.

Skills
        Team working spirit.
        Be initiative, ability to analyze and learn
        Team and result orientation are required.
        Know how to share knowledge with other colleagues.

Foreign Language:
        Good speaking and writing skills in English

Education:
        Bachelor of Science (Electrical Engineering)



SoC  
Senior Design Engineer
Location :shanghai/hangzhou

Key Responsibilities:

  • Preparation and     review of functional and design specification for SoC (ASIC/FPGA)
  • Prove logical     functionality and ASIC/FPGA code design/implementation.
·
Coding of SoC functionality form top-level down to blocklevel
  • Verification and     simulation of needed functionality on block level
  • Make test plan and     test strategy. Ensure effective testing and high quality product delivery.
  • Participate in     system requirement and architecture review.
  • Generating the test     bench environment for the verification
  • Responsible for test     planning, test case definition.
  • Responsible for test     environment setup and test automation tool implementation
  • Prepare and review     System-on-Chip development documentations and application documents
·
Working as the technical point of contact on the ASIC/FPGAarea.
Job Requirements:

SoC development & Methodology
  • 3+ years of SoC     (ASIC/FPGA) design experience
  • Very good     VHDL/Verilog knowhow and coding and modeling experience
  • Complete     understanding of the SoC (ASIC/FPGA) design flow and process.
  • Knowledge of SoC     (ASIC/FPGA) design and verification tools.
System
One to Two skills as mentioned below is required:
  • Solid background in Cellular networks and 2G and 3G     technology
  • Good knowledge on     TDM and Packet (IP/Ethernet) based telecommunication network solution
  • Microwave radio transport and related telecommunication     network solution knowhow
·
Detailed understanding of SDH and PDH technology andinterfaces
Experience
  • 3+ years experience in the     R&D of Telecommunication Networks or Communication industry.

Education/Skills
  • Bachelor/Master of Science (Electrical Engineering)
  • Innovative thinking and team working spirit.
  • Be initiative,     capable to analyze and learn
  • High team and result     orientation are required.
  • Know how to share knowledge     with other colleagues.
  • Fluent speaking and writing skills in English


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